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A Novel High Speed FPGA Architecture Design for FIR Filter


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  • Product Description

This edition of A Novel High Speed FPGA Architecture Design for FIR Filter presents the details of hardware implementation of linear phase FIR filter using merged MAC architecture. Speed of convolution operation of FIR filter is improved using merged MAC architecture.In order to improve the speed of the multiplication process within the computational unit;there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block.For implementation of this stage require addition of large operands that involve long paths for carry propagation.The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits.My objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device(XC3S400 PQ-208).The implemented FPGA architecture should help to design new efficient FIR architecture for high speed computation operation in Microprocessor &in DSP,and should be especially useful to students in VLSI field.

Product Specifications
SKU :COC62261
AuthorSachin Jadhav
Number of Pages108
Publishing Year16.12.2014
Edition1 st
Book TypeElectronics & communications engineering
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-08-05 00:00:00