The work presented in this book gives a glimpse into the various stages involved in the development of a Silicon Drift Detector (SDD) with on-chip JFET. The development of the SDD was carried out in phased manner, with the proto-type development being carried out at the Indian Institute of Technology-Bombay (IIT-B) followed by development of commercial grade SDDs at Bharat Electronics Ltd., Bangalore (BEL). Simulations in TCAD (device and process) were employed to arrive at optimized parameter values for the SDD with on-chip JFET. Various different kinds of SDDs and JFETs were designed to study the effect of a variation in design parameters on the performance parameters. The fabrication process for proto-type SDD was formulated for achieving a high breakdown voltage (>100V) coupled with a low leakage current achievable at IIT-B. Further, designs of the SDD with on-chip JFET were generated for fabrication at BEL. Fabrication of both SDD and JFET over high resistivity Silicon posed a significant technological challenge mitigated by process optimization in TCAD.