Modern integrated circuits depend on controlling relative timing of signals with picosecond accuracy. Their burgeoning complexity requires many approximations during design. Relatively large design margins are required to account for variations due to manufacturing tolerances. Voltage and temperature variations, intentional or incidental, may also affect signal timing and cause timing errors. Adaptive Delay Sequential Elements (ADSEs) are intended to correct timing errors whether they are caused by manufacturing tolerances, modeling approximation, or voltage/temperature variations. This book starts with an introduction to adaptive techniques using floating gates in standard CMOS processes and discusses how to augment sequential elements with Adaptive Clock Generators. It also covers methods for selective adaptation of embedded sequential elements and demonstrates applications in clock scheduling and peak power minimization. Self-tuning techniques and their algorithmic properties are also discussed. This book is intended for designers and researchers of processors and other VLSI circuits.