This research focuses on the design and characterization of a high performance single element of SPAD in state of the art standard deep sub-micrometer CMOS technology. This standard CMOS technology is the key factor of lowering the cost of the CMOS SPAD Imagers. Special effort was put on achieving the correct design for minimizing the detector’s noise, which in SPADs termed as the Dark Count Rate (DCR), and maximizing its quantum efficiency, termed Photon detection efficiency (PDE). The tested designs were fabricated in standard 180nm CMOS technology. The electro-optical measurements and characterizations were accompanied with appropriate simulations that were made with computer software, as well as with theoretical analysis. In most cases, the simulations on the designs were made prior the fabrication, allowing focusing on designs of interest, which proved to achieve the best results, and further understanding of SPADs operation.