Call Us 080-41656200 (Mon-Sat: 10AM-8PM)
Free Shipping above Rs. 1499
Cash On Delivery*

CMOS Low Power Analysis

 

Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
Delivery in :  10-12 Business Days

 

Check Your Delivery Options

 
Rs. 3,651

Availability: In stock

 
  • Product Description
 

In this thesis leakage reduction techniques like stack forcing, multiple threshold CMOS, variable threshold CMOS are explored, that mitigate leakage in circuits, operating in the active mode at various temperatures. Also, implications of technology scaling on the choice of techniques to mitigate total leakage are closely examined. The result is guidelines for designing low-leakage circuits in nanometer technology nodes. Logic gates in the 180nm, 130nm, 100nm and 70nm technology nodes are simulated and analyzed. Here delay analysis of various logic circuits are also examined.

Product Specifications
SKU :COC82799
AuthorVijay Sharma
LanguageEnglish
BindingPaperback
Number of Pages100
Publishing Year2011-06-01T00:00:00.000
ISBN978-3844382778
Edition1 st
Book TypeProduction engineering
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-10-08 00:00:00