As the operating voltage scales down with the technology, SRAM cells have focus at the stability. The 9T SRAM with inherent data stability and capability of reducing the leakage power is adopted to meet the stringent requirements of the low power designs. The circuit techniques used to reduce the power dissipation and delay of these components has been explored optimum power consumption is obtained. The key to data stability is the isolation between the bitlines and the data node in the 9T SRAM cell. The division of read and write sections provide reduction in the leakage power. In order to reduce the overall power dissipation of the chip the special hierarchical technique is been adopted for implementation of the 10:1024 row decoder. This design incorporates some of the circuit techniques used to reduce power dissipation and delay. The design is simulated at a clock speed of 3.33GHz. The read access time is found to be 0.85ns while the write access time is found to be 1.246ns at pre-layout simulations. The total leakage power dissipation is 20.579mW at pre-layout simulations. The SNM for 9T cell is 9.75% more than conventional 6T SRAM cell, with leakage power reduced to half.