Call Us 080-41656200 (Mon-Sat: 10AM-8PM)
Free Shipping above Rs. 1499
Cash On Delivery*

Design & Implementation of Programmable CRC Computation using FPGA

 

Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
Delivery in :  10-12 Business Days

 

Check Your Delivery Options

 
Rs. 3,718

Availability: In stock

 
  • Product Description
 

Good error control performance requires the scheme to be selected based on the characteristics of the communication channel. Consequently, error-detecting and correcting codes can be generally distinguished between random-error-detecting/correcting and burst-error-detecting/correcting. Cyclic codes have favorable properties in that they are well suited for detecting burst errors. The cyclic redundancy check (CRC) is an error detection technique that is widely utilized in digital data communication and other fields such as data storage, data compression, etc. The work presented in describes the FPGA implementation of a CRC Decoder that has the advantages of correcting more than one bit error. Since we are introducing the hardware implementation of CRC with error correction, our main concern is about the design of the CRC decoder with error correcting capabilities. Such an optimized circuit represents an attractive hard macro for environments requiring low cost hardware flexibility, and in emerging areas such as ISCSI-based SANs, where the flexibility to adopt emerging protocols offers a key advantage to vendors.

Product Specifications
SKU :COC62275
AuthorRameshwar Murade,Pavan Ingale and Rahul Kale
LanguageEnglish
BindingPaperback
Number of Pages104
Publishing Year06.08.2014
ISBN9783659162602
Edition1 st
Book TypeElectronics & communications engineering
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-08-05 00:00:00