A phase locked loop (PLL) plays significant role in analog and digital systems. It is a control system that generates an output signal in-phase of the input reference signal. This report has presented a low-power PLL implemented in 130nm CMOS technology for communication systems. The improved power efficient design of PLL consists of a phase detector; a charge pump, low pass filter, and bulk driven three stage ring VCO. The VCO is the main part PLL design. The proposed three, five and seven stages ring VCOs are presented in this report. The proposed three stage ring VCO shows better performance in terms of tuning range (917.43 MHz-4189.53 MHz) and power consumption (14.67µW). The output frequency of VCO shows almost linear relationship with the control voltage. The key design objectives of PLL are size, power consumption, lock range and frequency range of the VCO. The proposed low power, small area PLL has great potential in implantable bio-medical and wireless systems.