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Design of Reconfigurable Decoder for SRAM

Design of Reconfigurable Decoder for SRAM

 

Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
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  • Product Description
 

Decoder design consists of choosing the optimal performance circuit style, providing flexibility in configuration of different sizes, sizing of transistors, adding buffers and consideration of fan outs. In this work, high speed reconfigurable decoders of different styles are analyzed for different loads of memory blocks. The power dissipation, delay, frequency & Vdd of various logic styles are analyzed. Evaluation of delay is done by changing Vdd, Speed is improved and power dissipation is minimized by a sizing technique. The memory system plays crucial role in determining optimum performance, power, speed and cost of the simple to complex machines. To improve the access time in memory system, there is requirement of configurable logic block which can be used to select rows and columns of partitioned memory blocks. In a memory for accessing and locating any random data, address decoders are used. The decoder block is contributing in access time and power consumption of memories. In this work, a reconfigurable decoder is proposed to select fewer word lines and to avoid large word line / bit line capacitance.

Product Specifications
SKU :COC56672
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-06-08
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