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Design & Performance Evaluation of Arithmetic Units in DSM

 

Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
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  • Product Description
 

The core of every microprocessor, digital signal processor and data processing application-specific integrated circuit (ASIC) is its data path. It is often the crucial circuit component die area, power dissipation, and especially operation speed is of concern. At the heart of data-path and addressing units in turn are arithmetic units, such as comparators, adders, and multipliers. It is also a very critical one if implemented in hardware because it involves an expensive carry-propagation step, the evaluation time of which is dependent on the operand word length. The efficient implementation is a key problem in VLSI design. As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior studies have shown that chip operating frequency and leakage power can have large variations due to fluctuations in transistor gate length and sub-threshold voltage. This work presents the study on characterizing and analyzing the delay performance of various arithmetic units in CMOS digital circuits.

Product Specifications
SKU :COC56716
AuthorHiral Shah
LanguageEnglish
BindingPaperback
Number of Pages88
Publishing Year2012-08-14T00:00:00.000
ISBN978-3659216398
Edition1 st
Book TypeElectronics & communications engineering
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-06-08 00:00:00