The objective of this thesis is to design an All Digital Phase Locked Loop (ADPLL) to align the higher frequency signal at the output of the PLL with its input. This work presents a low power All Digital Phase Locked Loop (ADPLL) for the video applications. The ADPLL has wide range of operating input frequency from 10 kHz to 150 kHz. The output range of ADPLL is from 10 MHz to 300 MHz can be used for a variety of applications. The circuit of ADPLL is designed in a CMOS 65 nm technology using a supply voltage of 1 V. This project is designed using Cadence and MATLAB.