This work focuses on system level design strategies and techniques for circuit level implementations that facilitate low-power RFICs in bulk CMOS. Ultimately, the goal of this work is to enable the design of inexpensive and completely integrated circuits that consume so little power that they can be self-powered while communicating by means of an integrated antenna. As an application example, the design and implementation of a unique low-power integrated FM transceiver is presented. The transceiver is a completely new topology, using a modified PLL operated in both open-loop and closed-loop configurations, and using oscillator injection locking to accomplish FM demodulation with a minimum of circuitry. The receiver communicates across 1.75 m at 5.2 GHz while consuming 285 uW when duty cycled in a typical application.