While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid silicon diagnosis. This book targets test point insertions to detect more faults as well as to distinguish currently indistinguishable fault-pairs. This is achieved by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, a novel low-cost metric to identify such TD points is proposed. Further, a new DFT + DFD architecture is developed, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. In the other part, improving diagnosis in BIST environment is targeted. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories, response memory to store reference responses and fail memory to store failing responses. In this book, a novel architecture is proposed which requires only one additional memory and responses of only a small subset of available test patterns are stored.