This paper proposes an architecture that brings in a new dimension to instruction level parallelism. The operating system in today''s machines does all the decision making as to how the instructions in a task can be parallelized by deciding which task gets assigned to which core. The hardware support for exploiting instruction level parallelism is very small and has very little decision making power. Most recently dynamic scheduling of the instructions paved the pathway for major hardware changes and hence the decision making power shared. But the problem still persists. The operating has no direct help from the hardware and has to do most of the work at software level and hence the operating system has to be modified as the number of cores increase and the type of cores change. So a hardware support is a necessity in order to keep the operating system unchanged so that it doesn''t have to worry about the cores. The concept that I proposed plan to release the OS designer from this burden by introducing a Hardware Virtual Processor that will appear as a single processor to the OS, but inside it will be multiple specialized cores executing instructions in parallel.