Functional programming languages have been proposed to enhance the clarity of programs, to increase programmer productivity, and to reduce the difficulties of program verification. However, the lack of efficient implementation on conventional architectures prevents them from being widely accepted. This book presents an approach for solving this problem. A pipelined parallel reduction system has been developed on a multiprocessor system to realize hierarchical parallel processing. The correctness, reasonability and termination of the parallel execution can be guaranteed by enriching the lambda calculus lying behind functional languages. The scheduling strategies are also investigated for balancing processor loads and reducing processor idle ratio. The results of performance evaluation have exhibited the potential of the proposed functional architecture. The author believes this book would be a useful reference for those interested in understanding the implementation of functional languages.
|Number of Pages||160|
|Book Type||Computer hardware|
|Country of Manufacture||India|
|Product Brand||VDM Verlag Dr. Müller|
|Product Packaging Info||Box|
|In The Box||1 Piece|
|Product First Available On ClickOnCare.com||2015-07-31 00:00:00|