With rapid development in the area of RF and wireless communication, the interest in frequency synthesizers has grown rapidly in the last few years. Frequency synthesizer is used for local oscillator (LO) generation. In this thesis, our aim is to explore high-frequency low-power LO generation in CMOS technology. We focus on three most power-hungry blocks in a frequency synthesizer, which dominate the total power consumption due to their high-frequency operation, namely voltage-controlled oscillator (VCO), frequency divider and frequency multiplier, as these circuits are the bottleneck to achieve the above mentioned aim. Through reducing their power consumption, the total power consumption of the frequency synthesizer can be reduced significantly. Moreover, the phase noise of the frequency synthesizer is significantly dependent on the VCO and the frequency multiplier. These novel ideas are implemented in a 24-GHz frequency synthesizer. These designs should help those IC designers, who may be considering improving the performance of transceiver.