Scaling of silicon technology has entered an era of “material limited device scaling”, as fundamental physical limits have been reached with traditional CMOS materials. At the heart of the silicon MOSFET, new alternative high-k dielectric materials and metal gate electrodes are required to reduce gate leakage currents and decrease EOT. This book outlines the critical properties of potential high-k gate dielectric materials that provide a physically thicker layer to suppress the quantum mechanical tunneling through the dielectric layer. The emphasis is on the characterization of structural and electrical properties of such metal oxides. This book also presents the fundamentals of diffusion barriers in Cu metallization to address the issue of interconnect delay which is of increasing concern for advanced ULSI devices with rapid shrinkage of feature sizes. It highlights the effectiveness of potential candidates to meet current and future barrier requirements. The book will be of interest to those actively engaged in the field of material science and nanotechnology, focused on gate dielectric and copper metallization research.