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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style


Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
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  • Product Description

The main objective of this book is to provide new low power, low area and low power delay product solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS logic style gives best results over CMOS only and PTL only. A fine cost-performance ratio comparator design based on modified 1’s complement principle and conditional sum adder scheme using Hybrid PTL/CMOS logic style has been proposed in this report and the proposed design has small power dissipation, low power delay product and less area over various parameter ranges. Simulations are based on BSIM 3V3 90nm CMOS technology. It shows an 8-bit comparator of the proposed architecture only needs 154 transistors.

Product Specifications
SKU :COC92025
AuthorGeetanjali Sharma and Uma Nirmal
Number of Pages84
Publishing Year2013-09-13T00:00:00.000
Edition1 st
Book TypeElectronics & communications engineering
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-10-08 00:00:00
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