High speed data applications such as High-definition video streaming, Gigabit transmission always pose serious challenges to designers through stringent bandwidth, noise and power requirements. HD-video standards such as DVI and HDMI require gigabit data rate communication to support high resolution and sophisticated coding associated with them. However, clock signal sending in these transmission prove to be a bottleneck in achieving higher resolution. This book discusses the methods like serial interfacing ,differential signalling and clock recovery techniques to power optimize high speed transmission interface designs for the video applications. This work emphasizes upon achieving signal noise immunity, low power transmission, by carrying out low power implementations at system as well as sub-block level of design. The proposed transceiver implementation is carried out in a bottom-up approach with full-custom design flow using 0.18 µm CMOS technology. The analysis presented in this book would shed some light upon design methods of high speed CMOS circuits and loop stabalized systems & should prove useful to the practioners in Mixed-signal VLSI design.