Implementation of Floating Point Multiplier on Reconfigurable Hardware

Implementation of Floating Point Multiplier on Reconfigurable Hardware


Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
Delivery in :  10-12 Business Days

₹ 3,651

Availability: Out of stock


Delivery :

5% Cashback on all Orders paid using MobiKwik Wallet T&C

Free Krispy Kreme Voucher on all Orders paid using UltraCash Wallet T&C
Product Out of Stock Subscription

(Notify me when this product is back in stock)

  • Product Description

Foating point operations are hard to implement on reconfigurable devices because of their complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high level of accuracy in their calculations. Therefore VHDL programming for IEEE single precision floating point multiplier module have been explored. Various parameters i.e. combinational delay (Latency), chip area (number of slices used), modeling formats, memory usage etc have been analyzed while implementing the floating point multiplier on reconfigurable hardware. Analyzing the various parameters will provide with the information that Vertex4 will consume less chip Area i.e. 663 with reduced latency i.e. 49.906 ns as compared with the other FPGAs i.e. Spartan 2, Spartan 2E, Spartan 3, Spartan 3E, Virtex, Virtex 2, Virtex 2P, and Virtex E. Floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, the main emphasis is on the implementing it effectively such that it uses less combinational delay with high Speed.

Product Specifications
SKU :COC85865
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-10-08
0 Review(s)