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Low Power Latch Designs in Subthreshold Region


Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
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  • Product Description

In recent years, low power design has become one of the focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book presents pre-layout and post-layout simulations of existing 8T Latch and proposed latch designs in sub-threshold region. The proposed circuits consist of pass transistor gate logic. Proposed designs are area efficient so useful for portable devices. The proposed designs remarkably reduce power consumption and delay hence reduces power-delay product (PDP). Comparison with the existing design and proposed latch designs are performed at 65nm and 45nm to show technology independence. Comparative simulation results show that proposed 7T latch design with delay is better choice for portable applications. Therefore, the proposed 7T latch design with delay proves to be a viable option for low power and energy efficient applications.

Product Specifications
SKU :COC56696
AuthorKrishna Gopal Sharma,Abhilasha Choudhary and Tripti Sharma
Number of Pages80
Publishing Year2012-06-18T00:00:00.000
Edition1 st
Book TypeElectronics & communications engineering
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-06-08 00:00:00