Low Power Self-timed Size Optimization for an Input Data Distribution


Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
Delivery in :  10-12 Business Days

₹ 4,165

Availability: Out of stock


Delivery :

5% Cashback on all Orders paid using MobiKwik Wallet T&C

Free Krispy Kreme Voucher on all Orders paid using UltraCash Wallet T&C
Product Out of Stock Subscription

(Notify me when this product is back in stock)

  • Product Description

Power conservation has become an increasingly important issue among modern digital circuit designers. As the digital technology evolution takes us into the 21st century coupled with ground breaking system performance, the power consumed by these circuits are at record highs. In fact, power dissipation or energy loss in the form of heat is reaching levels comparable to nuclear reactors. The negative affect associated with the power dissipation compromises or in many cases, impair chip reliability and life expectancy. Over the past decade, research in this area has eased but not solved this power issue. Many solutions involved increasing chip parameter size to ease the chips density that has lead us to this hot spot. However, as the demand for portable electronic devices rise, scaling technology forces us to deal with this problem. Remarkably enough, if research does not produced a technique to break through the “power wall”, advancements in circuit technology will have reached its limits.

Product Specifications
SKU :COC92970
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
0 Review(s)