Video compression is an active area for potential research. Due to the limitations in the available bandwidth and storage space for high quality multimedia content like - video broadcasting and DVD video data, video compression has become very much necessary to keep up the ever growing demand, yet maintaining the quality in decoded video. Motion Estimation technique in a video coder takes advantage of the temporal redundancy present in video data to achieve substantial compression. The block matching efficiency of the Motion Estimation algorithm, feasibility for hardware implementation and multiple frame storage delays are some of the key challenges faced in implementing a Motion Estimation block. In this work, a software model of Motion Estimation block for H.264 Advanced Video Coder is designed. One Step Search Motion Estimation algorithm is chosen for hardware modeling. The architecture of the model is designed to maximize the throughput of the system by using dual residual energy computation and comparison units for parallel processing of frame data. The hardware model is succesfully implemented and tested on Xilinx Virtex-4 FPGA.