Integrated, low-power, low-noise CMOS neural amplifiers have recently grown in importance as large microelectrode arrays have begun to be practical. This project aims to design a low power, low noise and low THD adjustable gain neural amplifier for multichannel neural recording chip for use with cuff-based recording microelectrodes. The neural amplifier is designed using AMS CS 0.35um technology for supply voltage of 3V. With overall power consumption less than 0.5mW, it is able to measure three different types of neural signal with adjustable gain between 50 to 10000 and bandwidth vary from few hundred hertz up to 10kHz. The input- referred noises are below 45nV/sqrt(Hz) at 1kHz in all the three different signals cases. THD varies as the gain changes, in general lower the gain will have better the THD. Two different neural amplifier topologies (single op- amp and two op-amp) have been designed and simulated separately in CADENCE for three different gains situations. It was found that the two op-amp topology design has better overall performance than the single op-amp design despite it is more power consuming.
|Number of Pages||72|
|Book Type||Electronics & communications engineering|
|Country of Manufacture||India|
|Product Brand||LAP LAMBERT Academic Publishing|
|Product Packaging Info||Box|
|In The Box||1 Piece|
|Product First Available On ClickOnCare.com||2015-10-08 00:00:00|