☰ Category

Optimisation of Grooved Gate MOSFETS for SUB-100 NM VLSI Technology


Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
Delivery in :  10-12 Business Days


Check Your Delivery Options

Product Out of Stock Subscription

(Notify me when this product is back in stock)

Rs. 4,396

Availability: Out of stock

  • Product Description

The short-channel and hot-carrier effects that arise when MOSFET devices are scaled down to very short channel lengths is a major topic of research in the area of VLSI technology. Grooved gate MOSFETS alleviate many of these. Here a systematic study of the major electrical characteristics of grooved gate device is done at gate lengths of 100 nm. An optimised process flow is presented to overcome two of its major drawbacks - higher gate-to-source/drain parasitic capacitance and lack of a self-aligned and integrated gate structure. The resulting device exhibits significantly enhanced characteristics. An analytical model for the gate-to-source/drain capacitance characteristics of the grooved gate device is then presented. It features an extrinsic capacitance model that incorporates the strong bias dependence of overlap capacitance and deals with the issues involved in optimisation and analysis of not only such novel device structures but source/drain engineered conventional planar devices also. This work should be especially useful to professionals and students in Microelectronics field who are engaged in processing, characterization and modelling of deep sub-micron VLSI devices.

Product Specifications
SKU :COC56410
AuthorSreelal Sreedharan Pillai and Samudra Ganesh Shankar
Number of Pages128
Publishing Year2012-06-20T00:00:00.000
Edition1 st
Book TypeElectronics & communications engineering
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-06-08 00:00:00
0 Review(s)