Field programmable gate arrays (FPGAs) have revolutionized the way digital systems are designed and built over the past decade. With architectures capable of holding tens of millions of logic gates on the horizon and planned integration of configurable logic into system-on-chip platforms, the versatility of these programmable devices is expected to increase dramatically. Placement is one of the vital steps in mapping a design onto FPGA in order to take the best advantage of the resources and flexibility provided by it. Here, techniques of Placement Optimization have been tested on MCNC Benchmark circuits. PSO (Particle Swarm Optimization) has been implemented on circuit netlist with different cost functions to verify efficiency of optimization. Furthermore, lazy descent has been introduced into the algorithm to impede premature convergence. This book will be especially helpful to research scholars and students of electronics seeking superior heuristic optimization techniques for FPGA circuit placement. Further work on routing optimization might lead to a commercially viable mapping algorithm.