Optimizing Assertion Sets Using Logic Synthesis Techniques

Optimizing Assertion Sets Using Logic Synthesis Techniques


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The result looked at first as unexpected, however, an attentive reflection reveals that in a formal verification setting, adding more dependencies to an assertion reduces the number of states that the formal verification tool needs to explore in order to prove whether the assertion is true or false. This also explains why the merged Karnaugh maps did exceptionally well while the heuristics test did poorly in comparison. In a formal setting, merging Karnaugh maps allowed IFV to prove the assertion set 4 times faster than the initial non-optimized set of non-redundant assertions.

Product Specifications
SKU :COC65685
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-07-08
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