This book presents the power optimization consumption for Network-on-Chip (NoC) architecture based on network partitioning (NP). The new methodology is proposed to reduce the total power consumption in NoC by utilizing network partitioning (NP) technique to solve the NoC’s problem so that it gives a satisfactory performance with the use of high speed, complex ICs in mobile and portable applications. The development of NoC communication power is to estimate the total power consumption in NoC-based communication system. This algorithm will consists of vertex mapping to Processing Elements (PE), delay optimization and node mapping. This power consumption mapped on the mesh topology which verified through mpeg-4 video application as a case study.