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PVT Variation Aware Low Power Vedic Multiplier Design For DSPs on FPGA

PVT Variation Aware Low Power Vedic Multiplier Design For DSPs on FPGA

 

Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
Delivery in :  10-12 Business Days

 
₹ 3,718

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  • Product Description
 

As the communication and signal processing industries are proliferating the demand for the multipliers is continuously increasing at a rapid rate. For researchers, to develop high speed and power efficient multiplier has been a grave matter of concern. Reduction in the power consumption and delay of a multiplier circuitry is expected to cause a revolution in the field of electronics and communication.The performance of system is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Hence, optimizing the speed and power consumption of the multiplier is a major design issue. There is need of development of high speed and low power multiplier for digital signal processing algorithms. From the previous research, it has been concluded that Vedic multiplier are more efficient than conventional multiplier. In this work, low power Vedic multiplier has been proposed.

Product Specifications
SKU :COC54798
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-06-08
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