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Response Data Compression Techniques in Digital Circuit Testing

 

Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
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  • Product Description
 

Today, digital logic circuits are essential embedded parts of devices that are critically important due to impact on public safety. Such devices include transportation, human implants and critical systems’ management where Fault-Tolerant (FT) concept is the bottom line. To implement the concept of FT it is essential to test the system accurately to measure all the critical parameters of a dependable system. Challenges of testing has become more difficult due to ubiquitous and complexity of digital systems. Exhaustive testing is impossible and ATEs are not commonly affordable that led to the design concepts of DFT and BIST techniques. Due to the problems of storing huge response data the data compression techniques (RDC) like One's Count, Transition Count, Syndrome Testing, Walsh Spectra Coefficients, Signature Analysis, etc. are used in practicing testing. However, the problems of Aliasing are inevitable in RDC techniques. Embodied in this book is the study and evaluations of the effectiveness of various RDC techniques while applied individually. The results of extended study and evaluations of combinations of different RDC techniques are also part of the contents of the book.

Product Specifications
SKU :COC62327
AuthorJaber Al-Balushi and Afaq Ahmad
LanguageEnglish
BindingPaperback
Number of Pages96
Publishing Year11.11.2014
ISBN9783659239618
Edition1 st
Book TypeElectronics & communications engineering
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-08-05 00:00:00
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