Soft error is a significant reliability concern for nanometer technologies. Shrinking feature sizes, lower voltage levels, reduced noise margins, and increased clock frequency improves the performance and lowers the power consumption of integrated circuit. But it causes the integrated circuit more susceptible to soft error that can corrupt data and make systems vulnerable. The ‘device shrinking’ reduces the soft error tolerance of the VLSI circuits, as very little energy is needed to change their states. In digital systems, where the reliability is a great concern, the impact of soft errors may be very catastrophic. Safety critical systems are very sensitive to soft errors. A bit flip due to soft error can change the value of critical variable. And consequently the system control flow can completely be changed which may lead to system failure. To minimize the soft error risks, critical blocks are identified by criticality analysis of the blocks and ranking among them. Highest ranked blocks are considered as critical block. Refactoring is applied to minimize the criticality of the critical blocks. Then a novel methodology is proposed to detect and recover from soft errors.