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Study and Analysis of Vedic Multipler and 16 Bit Arithmatic Unit


Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
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  • Product Description

This study is based on design and implementation of a 16 bit Arithmetic module, which uses Vedic Mathematics algorithms.The Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E tools. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. Another Model of Vedic Multiplier is proposed by using compressor adder for 8 bit and 16 bit Multiplication that has improved the performance of Multiplier.

Product Specifications
SKU :COC62294
AuthorKrishna Lal Baishnab,Ram Kumar and Radhe Shyam Gupta
Number of Pages92
Publishing Year03.10.2014
Edition1 st
Book TypeElectronics & communications engineering
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-08-05 00:00:00