This work introduces an approach to automatically synthesize Simulink diagrams into asynchronous circuits. It is based on the CodeSimulink co-design environment, a tool developed at Politecnico di Torino able to convert Simulink diagrams into synchronous implementations. Such environment has been extended in two different ways in order to integrate it with conventional FPGA and ASIC flows. The system generated with FPGAs as target is based on bundled-data implementation, which needs special care during both synthesis and placement in order to maintain circuit correctness. Simulink diagrams are compiled into standard VHDL and synthesized with conventional tools provided by chip manufacturers. The obtained code is constrained to avoid unwanted synthesis optimizations and constrained to implement the "equipotential region" necessary to synthesize correct self-timed designs. The ASIC implementation uses the Timeless Design Environment by Handshake Solutions, a commercial tool chain able to synthesize Haste specifications into asynchronous logic. Experimental test showed good results generating smaller circuits even than hand-written code.