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Synthesis of High Performance Low Power CMOS Circuit Design


Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
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  • Product Description

Latches and flip-flops used in low power sequential circuits are discussed in this book. A synthesis technique for power optimization in combinational logic circuits has been described. A flip flop has been proposed to reduce power consumption in CMOS circuits. A latch has been proposed which is evaluated from the standard ultra voltage latch for low power application. Simulation results show that the proposed latch has the lowest power consumption with no speed penalty. The significant power and area savings can be achieved by using proposed design.

Product Specifications
SKU :COC56603
AuthorNeelam Swami
Number of Pages92
Publishing Year2012-07-20T00:00:00.000
Edition1 st
Book TypeElectronics & communications engineering
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-06-08 00:00:00