The Zero Instruction Set Computer (ZISC) is an integrated circuit containing a Restricted Coulomb Energy neural network that employs parallelism to execute many operations in very short time periods. We evaluate the computational capability of this device in the context of using it for image pattern recognition, seeking to consume less time than a computer without the ZISC. We discuss the feasibility of using a correlation coefficient calculation to determine if a portion of an image is a match to a given pattern, and describe a serial algorithm to use on a computer without the ZISC. We also discuss four algorithms that are implemented on a computer that accesses a ZISC via the PCI bus. The results of our experiments show that the performance of our ZISC-based algorithms is indeed an improvement over the serially-implemented algorithm.