Timing and Signal Integrity Issues with VLSI Interconnects


Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
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  • Product Description

This book discusses the timing and signal integrity issues with VLSI interconnects in sub-nanometer designs. Starting with the basics of interconnect equivalent circuit model it describes the RLC equivalent models of interconnects, their extraction methodologies, and circuit simulation for timing and signal integrity analysis. With enormous analysis results for different technology nodes the importance of on-chip inductive effects has been discussed. The sample simulation model along with the SPICE netlist for timing and signal integrity analysis has been provided in the appendix. The book will be useful to the teachers, students, and researchers who are involved in modeling and analyzing the interconnects in future generation VLSI technology nodes. The book comprises four chapters and one appendix.

Product Specifications
SKU :COC82156
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
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