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Universal Verification Methodology Based Verification Environment

 

Marketed By :  LAP LAMBERT Academic Publishing   Sold By :  Kamal Books International  
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Rs. 2,749

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  • Product Description
 

Ever increasing silicon design complexity and transistor density, product differentiation and time to market are major factors creating huge pressure on complete design flow. This book covers Verification phase by describing the concepts of Universal Verification Methodology (UVM) and by presenting a pragmatic approach of developing efficient and unified advanced verification environment at all levels using Universal Verification Methodology along with Assertion based verification, hardware acceleration and Transaction Level Modeling. This book is written primarily for verification engineers performing verification of complex IP blocks or entire system-on-chip (SoC) designs. However, much of material will also be of interest to SoC project managers as well as designers to learn more about verification. Furthermore, this book includes detailed information about verification environment for one case which can be easily used as reference for other cases.

Product Specifications
SKU :COC75339
AuthorAbhishek Jain
LanguageEnglish
BindingPaperback
Number of Pages140
Publishing Year2014-01-19T00:00:00.000
ISBN9783659476044
Edition1 st
Book TypeComputing & information technology
Country of ManufactureIndia
Product BrandLAP LAMBERT Academic Publishing
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-10-08 00:00:00
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