AMBA AXI-04 is an IP protocol which supports 16, masters and slaves interfacing. AMBA AXI-04 system consists of master, slave and interconnect. The system consists of five channels namely write address channel, write data channel, read address channel, read data channel, and write response channel. The AXI-04 update to AXI-03 includes the following: support for burst lengths up to 256 beats, updated write response requirements, removal of locked transactions and AXI-04 also includes information on the interoperability of components. The work aims to design master, slave and interconnect modules according to AMBA AXI-04 protocol, modelled in Verilog HDL. The simulation results for read and write operation of address and data are shown in VCS tool. The master and slave components have an interface with the test layer which provides necessary stimulus. This test layer is built exclusively to initiate the transaction and provide the meaningful inputs to master and slave. The operating frequency is set to 100MHz. Two test cases are run to perform multiple read and multiple write operations. To perform single read operation the module takes 160ns and for single write operation 565ns.