Call Us 080-41656200 (Mon-Sat: 10AM-8PM)
Free Shipping above Rs. 1499
Cash On Delivery*

WIRE AWARE CACHE ARCHITECTURE

 

Marketed By :  VDM Verlag Dr. Müller   Sold By :  Kamal Books International  
Delivery in :  10-12 Business Days

 

Check Your Delivery Options

 
Rs. 4,396

Availability: In stock

 
  • Product Description
 

Technology scaling has resulted in a steady increase in transistor speed. However, unlike transistors, global wires that span across the chip show a reverse trend of getting slower with shrinking process. Modern processors are severely constrained by wire delay and the widening gap between transistors and wires will only exacerbate the problem. Following the traditional design approach of adopting a single design point for all global wires will be suboptimal in terms of both power and performance. VLSI techniques allow several wire implementations with varying latency, power, and bandwidth properties. The dissertation advocates exposing wire properties to architects and demonstrates that prudent management of wires at the microarchitectural level can lead to significant improvement in power and delay characteristics of future communication bound processors. A heterogeneous interconnect (composed of wires with different latency, bandwidth, and power characteristics) is proposed that leverages varying latency and bandwidth needs of on-chip global messages to alleviate interconnect overhead.

Product Specifications
SKU :COC47753
AuthorNaveen Muralimanohar
LanguageEnglish
BindingPaperback
Number of Pages148
Publishing Year2010-03-17T00:00:00.000
ISBN978-3639241372
Edition1 st
Book TypeElectronics & communications engineering
Country of ManufactureIndia
Product BrandVDM Verlag Dr. Müller
Product Packaging InfoBox
In The Box1 Piece
Product First Available On ClickOnCare.com2015-04-08 00:00:00
0 Review(s)